1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device with a mode register and a method for controlling both an entry into and a release from a deep power down (referred to as a xe2x80x9cDPDxe2x80x9d hereinafter) in the semiconductor memory device.
2. Description of the Prior Art
As generally known in the art, with the increase in the use of portable devices such as personal digital assistants or notebook computers, demand has risen for low power memory. A dynamic random access memory (referred to as a xe2x80x9cDRAMxe2x80x9d hereinafter) tends to use an external power supply of 2.5 V instead of a conventional external power supply of 3.3 V, and has a data input/output signal of 1.8 V instead of a conventional data input/output signal of 3.3 V, in order to embody the low power memory. Low power DRAMs having a self refresh cycle adjustment function and a partial self refresh function have been developed. The self refresh cycle adjustment function is a function which adjusts a self refresh cycle using the characteristic of the semiconductor memory device that a data duration time of a data cell varies according to a change in its temperature. The partial self refresh function is a function which does not refresh a total cell array but partially refreshes only necessary parts of the cell array.
A conventional DRAM typically includes an active mode and a standby mode as normal operation modes. The standby mode lowers a current driving performance of an internal power supply voltage generator as a low power mode. However, in order to further decrease power consumption, DRAMs operating in the DPD mode have been developed. The power consumption in the DPD operation mode is less than that in the standby operation mode. In such DRAMs, the current driving performance of the internal power supply voltage generator is not simply lowered, the internal power supply voltage generator does not operate at all, and only a clock buffer for receiving a clock signal operates, thereby minimizing power consumption of the DRAMs.
A conventional DRAM enters the DPD mode in synchronization with a clock signal CLK based on a predetermined combination of various different command signals, for example, when a clock enable signal CKE is at a low level, a row address strobe signal RASB and a column address strobe signal CASB are at high levels, and a write enable signal WEB and a chip select signal CSB are at low levels. When the clock enable signal CKE goes to a high level, the conventional DRAM is released from the DPD mode. After the release from the DPD mode, a normal operation is performed through a power sequence for a predetermined time, for example, 200 xcexcs. At the beginning of a power up, the clock enable signal CKE, the row address strobe signal RASB, the column address strobe signal CASB, the write enable signal WEB, and the chip select signal CSB are supplied from outside together with a power supply signal. Since circumstances of the CKE, RASB, CASB, WEB, and CSB signals are different from one another, ramp_up slopes thereof become different from one another. At any time during the beginning of power up, a case in which the levels of these signals satisfy the conditions for an entry into the DPD mode as described above can occur. In that case, an undesirable entry into the DPD mode may happen. Internal power supply is turned off, so that the semiconductor memory device does not perform a normal operation.
Accordingly, the present invention has been made to solve the above-mentioned problems occurring in the prior art, and an object of the present invention is to provide a semiconductor memory device with a mode register that prevents the semiconductor memory device from undesirably entering into an DPD mode during the beginning of a power up.
Another object of the present invention is to provide a method for controlling a DPD mode in a semiconductor memory device with a mode register that stably performs an entry into and a release from a DPD mode in the semiconductor memory device.
In accordance with an aspect of the present invention, there is provided a semiconductor memory device with a mode register, the semiconductor memory device comprising: an internal power supply voltage generator for generating an internal power supply voltage of the semiconductor memory device based on an external power supply voltage when the external power supply voltage is applied to the internal power supply voltage generator; a clock buffer for receiving and buffering external clock and clock enable signals in order to generate internal clock and clock enable signals; a command decoder for receiving the internal clock and clock enable signals from the clock buffer, for receiving an external command signal, and for generating either an intermediate deep power down mode entry signal instructing the semiconductor memory device to enter into a deep power down mode or a mode register setting signal commanding a setting of the mode register according to a predetermined combination of the internally received clock and clock enable signals with the received external command signals; a mode register setting latch circuit for latching the mode register setting signal from the command decoder when the mode register setting signal is received after a stabilization of the external power supply voltage; and a deep power down mode controller for receiving the intermediate deep power down mode entry signal from the command decoder, for generating a final deep power down mode entry signal when the deep power down mode controller receives the mode register setting signal from the command decoder, and for outputting the finally generated deep power down mode entry signal to the internal power supply generator.
Preferably, the clock buffer circuit operates by an external power supply voltage, and generates the deep power down mode release signal instructing the semiconductor memory device to be released from a deep power down mode using the external received clock enable signal, and for providing the generated deep power down mode release signal to the deep power down mode controller. The internal power supply voltage generator generates an external power supply voltage detecting signal having a first level when the external power supply voltage is stabilized, and outputs the generated external power supply detecting signal to the mode register setting latch circuit. The mode register setting latch circuit latches the mode register setting signal from the command decoder when the external power supply detecting signal reaches the first level.
The mode register setting latch circuit includes a first inverter for receiving and inverting the external power supply detecting signal; a first NAND gate for receiving an output signal of the first inverter as a first input signal; a second inverter for receiving and inverting the mode register setting signal; a second NAND gate for NANDing an output signal of the second inverter and an output signal of the first NAND gate to generate an output signal to be become a second input signal of the first NAND gate; and a third inverter for receiving and inverting an output signal of the first NAND gate and outputting the inverted signal as an output signal of the mode register setting latch circuit.
The deep power down mode controller includes a third NAND gate for NANDing the intermediate deep power down mode entry signal from the command decoder and an output signal of the mode register setting latch circuit; and a fourth inverter for receiving and inverting an output signal of the third NAND gate. The deep power down mode controller includes a fifth inverter for receiving and inverting an output signal of the fourth inverter; an NMOS transistor including a gate for receiving an output signal of the fifth inverter and a source being grounded; a latch section including first and second input terminals which are connected to a drain of the NMOS transistor and an output terminal of the fourth inverter, respectively; and a NOR gate for receiving the deep power down mode release signal and an output signal of the latch section as two inputs.
In accordance with another aspect of the present invention, there is provided a semiconductor memory device with a mode register, the semiconductor memory device comprising: a deep power down decoder for receiving external clock, clock enable, and command signals and for generating an intermediate deep power down mode entry signal instructing the semiconductor memory device to enter into a deep power down mode in response to a predetermined combination of the received external clock, clock enable, and command signals; a mode register setting decoder for receiving the external clock and command signals, and for generating a mode register setting signal instructing a setting of the mode register in response to a predetermined combination of the received external clock and command signals; a mode register setting latch circuit for latching the mode register setting signal from the mode register when the mode register setting signal is received after a stabilization of an external power supply; and a deep power down mode controller for receiving the intermediate deep power down mode entry signal from the deep power down decoder, and for generating a final deep power down mode entry signal when the mode register setting signal is received from the command decoder.
In accordance with a further aspect of the present invention, there is provided a method for controlling a deep power down mode in a semiconductor memory device with a mode register, the method comprising the steps of: (i) receiving external clock, clock enable, and command signals, and generating an intermediate deep power down mode entry signal instructing the semiconductor memory device to enter into a deep power down mode or a mode register setting signal commanding a setting of the mode register according to a predetermined combination of the received internal clock and clock enable with the external command signals; (ii) latching the mode register setting signal when the mode register setting signal is received after a stabilization of the external power supply voltage; and (iii) generating a final generated deep power down mode entry signal when the intermediate deep power down entry and mode register setting signals are received.